In response to electronic products that are being developed to have multi-functionality, high electrical performance and high operating speed nowadays, semiconductor manufacturers endeavor to provide semiconductor devices integrating a plurality of chips or packages as required for the electronic products.
FIG. 1 shows a stack structure of semiconductor packages disclosed in U.S. Pat. No. 5,222,014. A ball grid array (BGA) substrate 11 with bond pads 110 formed on an upper surface thereof is provided, and a semiconductor chip 10 is mounted on the BGA substrate 11 and encapsulated by an encapsulant 13, so as to form a first semiconductor package 101. Then, a second semiconductor package 102 is mounted and electrically connected to the bond pads 110 of the substrate 11 of the first semiconductor package 101 by solder balls 14, so as to form a stack structure of semiconductor packages.
However, in the above stack structure of semiconductor packages, when the second semiconductor package is mounted to the bond pads of the substrate of the first semiconductor package by the solder balls and is subjected to a reflow process to make the solder balls bonded and electrically connected to the bond pads, misalignment of the second semiconductor package with respect to the first semiconductor package usually occurs because the solder balls become melted and softened during the reflow process, thereby leading to a failure of electrical connection between the first and second semiconductor packages.
Accordingly, U.S. Pat. No. 6,987,314 discloses another stack structure of semiconductor packages as shown in FIG. 2. In this stack structure, a pre-solder material 22 is disposed on bond pads of a substrate of a first semiconductor package 201. When a second semiconductor package 202 is mounted on the first semiconductor package 201 by solder balls 24 that are reflowed to the pre-solder material 22, self-alignment between the pre-solder material 22 and the solder balls 24 can properly position the second semiconductor package 202 on the first semiconductor package 201. However, the provision of the pre-solder material on the bond pads of the substrate of the first semiconductor package increases not only the fabrication costs but also complexity of the fabrication processes for the stack structure.
Taiwan Patent No. I250627 discloses another stack structure of semiconductor packages as shown in FIG. 3. In this stack structure, a second semiconductor package 302 is electrically connected to a first semiconductor package 301 by a plurality of solder balls 34, and infrared paste (IR paste) 35 is provided between a substrate 311 of the first semiconductor package 301 and a substrate 312 of the second semiconductor package 302. Then, infrared irradiation is performed to adhere the second semiconductor package 302 to the first semiconductor package 301 by the IR paste 35. However, the provision of the IR paste on the substrate of the first semiconductor package and performing the infrared irradiation to adhere the second semiconductor package to the first semiconductor package both undesirably increase the fabrication costs and complexity of the fabrication processes for the stack structure.
Therefore, the problem to be solved here is to provide a stack structure of semiconductor packages and a method for fabricating the same, so as to prevent the misalignment problem caused by a reflow process when using solder balls to electrically connect and stack semiconductor packages, and avoid increase in fabrication costs and process complexity due to the use of a pre-solder material disposed on bond pads of a substrate of a lower semiconductor package or due to the use of IR paste provided between substrates of upper and lower semiconductor packages.